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Apply before 31st December 2024!
Make your first step toward a successful career
All candidates will be notified about their application status in a timely manner, while the start is planned for beginning of March. Good luck with the interviews!

Analog Mixed-Signal Design and Verification Engineer

You will be a part of an analog design and modeling team, constituted of engineers with a different level of experience, from experts to juniors. Involvement in analog IP models development, model calibration (model vs schematic) and close interaction with other IC implementation teams in order to achieve IC implementation milestones. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows. Selected candidates will receive full training and support from our experienced engineers. The project can be a subject of a bachelor/master thesis or seminar paper.

  • Selected candidates will be engaged in:
  • Development of Verilog A/AMS models of AMS IP
  • Analog and mixed-signal circuits analysis
  • Development of AMS design verification environment
  • Using Cadence toolchain for AMS verification
  • Intern will receive full training and support from our experienced engineers.
  • Duration of internship is 4 months and will begin after exams or differently defined with candidate
  • Full time internship 40h a week or differently defined with candidate
  • Internship project can be subject of a bachelor/master thesis or seminar paper
  • Interns will receive monthly compensation
  • Company will provide accommodation if interns are outside of Belgrade or Novi Sad

Internship Timeline

1 week
(lectures + project)
Digital design
3-4 weeks
(lectures + Lab practice)
System Verilog and UVM
1 week
UVC creation of a given module
≈10 weeks
(2 lectures + Lab practice + Final model)
Analog modeling Verilog – AMS
2 weeks
Model integration into UVM environment
1 week
(lectures + project)
Digital design
3-4 weeks
(lectures + Lab practice)
System Verilog and UVM
1 week
UVC creation of a given module
≈10 weeks
(2 lectures + Lab practice + Final model)
Analog modeling Verilog – AMS
2 weeks
Model integration into UVM environment

Employee Benefits:

FULLY REMOTE​

PROFESSIONAL,
YOUNG & DYNAMIC TEAM​

PROFESSIONAL DEVELOPMENT
OPPORTUNITIES​

COMPETITIVE SALARIES
& BENEFITS​

ADDITIONAL HEALTH INSURANCE,
SPORT & SOCIAL ACTIVITIES​​

INTERNATIONAL WORK ENVIRONMENT &
TRAVELING OPPORTUNITIES​

Required Skills and Qualifications:

Final year student or fresh graduate with B.Sc. or M.Sc. degree in electrical engineering

Motivated, proactive, hard working

Relevant courses/knowledge: basics of analog electronics, VLSI basics

Skills: Familiar with basic analog circuitry, CMOS, and bipolar technology, VHDL or Verilog HDL language, Cadence tools knowledge is a plus

Good knowledge of English language

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Apply before 31st December 2024!
Make your first step toward a successful career

Apply Now!
All candidates will be notified about their application status in a timely manner,
while the start is planned for 3rd March 2025. Good luck with the interviews!

Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Kristina Radivojević
Recruitment and HR Specialist
CV Assistance